Making old chips better: Two-thirds of all chips sold in 2022 were at the 65 nm process node or larger, a decades-old technology.8 Taking those old chip designs and moving them to more advanced nodes (a “shrink”) makes them physically smaller and more power-efficient, and it doesn’t rely on obsolete fabrication equipment. Advanced AI tools allow chipmakers to effect these shrinks faster and cheaper.
Plugging the chip talent gap: About 2 million people work for the chip industry globally in 2022, but with the ongoing drive for chip self-sufficiency in the United States, European Union, and China, the sector needs to find a million more workers by 2030.9 Advanced AI tools will become increasingly important as a way of bridging the talent gap.
Chips go through three main design phases: system-level design, register transfer-level design (RTL), and finally physical circuit design. It is in this last phase where advanced AI tools can really shine.
Chip design optimizes three variables—power, performance, and area (PPA)—to produce a chip that minimizes electricity use, maximizes processing speed, and is as small as possible. Optimizing PPA with conventional tools is slow and labor-intensive: Design iterations can take weeks, and the iterations often improve PPA only slightly. It can take years to design a chip; implement the design in physical form; and evaluate, test, and simulate both the design and implementation.
Chips have billions of transistors, represented by modular blocks—which contain elements such as memory subsystems, compute units, control logic systems, and power sources—and standard cells. In highly complex chips, these modular blocks are connected by up to 50 kilometers of wires. When blocks aren’t optimally arranged, it takes more wiring and space to connect blocks. Unintended electric charges between components—which are called parasitics—can impede performance and sap power.
Advanced AI tools can test human designs by finding placement errors that increase power consumption, impede performance, or use space inefficiently; suggesting improvements; and then simulating and testing those. These tools learn from prior iterations to improve PPA until it reaches its limit. But what’s truly revolutionary is that advanced AI can do this autonomously, generating better PPAs than human designers using traditional EDA tools—and sometimes do it in hours with a single design engineer compared to weeks or months with an engineering team.
These advanced AI capabilities fall almost entirely into two categories: graph neural networks (GNNs) and reinforcement learning (RL). GNNs are a type of machine learning algorithm specialized for analyzing graphs—data structures that contain “nodes,” which can be any object, and “edges,” which define the relationship between nodes.10 Traditional deep learning neural networks struggle with graphs,11 but GNNs extract information from graphs, make useful predictions about their connections, and rearrange nodes while preserving the key relationships.12 Because chip structure is essentially graph-like—macro blocks and standard cells are node-like and the wires connecting them are edge-like—GNNs are ideal for analyzing and optimizing chips.
RL turns physical chip design into a graph optimization “game.” It’s the same technology Google used to defeat the human champion in the strategy board game Go, which is even more complicated than chess and was thought to be beyond AI’s abilities. Physical chip design is exponentially more complex still (figure 2), but RL tackles it in the same way. It trains on thousands of “games”—chip floor plans, which simulate chip designs to find the best PPA arrangements. The AI-generated floor plans are reinforced by a mix of rewards from the human designers for designs that optimize PPA, such as those that reduce wire length, congestion, density, power consumption, and area,13 and punishments for suboptimal designs. These reinforcements improve the RL system over time, teaching it to generate better designs autonomously.14